AEP experts collaborate with government, academia and industry to provide comprehensive flexible electronics capabilities that bridge the high-risk, resource-intensive gap between innovation and product development in an information-secure environment. Our world-class facility offers unique manufacturing pilot lines (150 mm wafer-scale and 370 x 470 mm sheet-scale) in a Class 10 clean room. We provide an information-secure environment for process, tool and materials development and evaluation. We also integrate sustainable microelectronics processing into all of our activities.

Backplane electronics design, fabrication, test and integration capability are all located within the AEP headquarters at ASU Research Park in Tempe. The center operates dedicated pilot line toolsets for technology development and for technology demonstrator production. The 6” wafer-scale Pilot Line tools are dedicated to R&D starts and support of the GEN II line including process development and improvement for advanced technology insertion. The GEN II 370 x 470 mm display-scale pilot line tools are dedicated to low-volume manufacturing.

Sponsor Services

• Integrated circuit (IC) design and development and fabrication of inorganic and organic thin film transistor (TFT) arrays
• Design for manufacturability with high yield and optimal circuit performance
• Early stage prototyping and low-volume production